1. Field of the Invention
The present invention relates to a NAND flash memory. In particular, the present invention relates to a semiconductor memory device which is capable of storing multi-value data in a memory cell.
2. Description of the Related Art
A NAND flash memory has a NAND cell, which is configured in the following manner. Specifically, all of the cells arrayed in the row direction are connected to a word line, and all of the cells arrayed in the column direction, or half of the cells thereof are serial-connected, and thus, the NAND cell is configured. The drain of each NAND cell is connected to a bit line via a select gate. Each bit line is connected to a write and read latch circuit. A write or read operation is collectively carried out with respect to all of the cells arrayed in the row direction, or half of the cells thereof (e.g., 2 to 4 K bytes). According to an erase operation, the threshold voltage of a memory cell is set to a negative voltage, and then, electrons are injected into the memory cell via a write operation, and thereby, the threshold voltage is set to a positive voltage (see, e.g., Jpn. Pat. Appln. KOKAI Publication No. 2004-192789).
The NAND flash memory has a plurality of serial-connected memory cells. For this reason, in a read operation, a non-select cell needs to be set to an on state, and thus, a read voltage (Vread) higher than the threshold voltage is applied to the gate of the cell. Therefore, the threshold voltage in the write operation never exceeds the voltage Vread. For this reason, in the write sequence, program and program verify read are repeated for each bit, and threshold distribution must be controlled not to exceed the voltage Vread. As a result, the write speed becomes slow.
In order to store a large capacity, a multi-value memory storing two bits or more in one cell has been developed. For example, if one cell is stored with two bits, four threshold distributions must be set. Compared with a memory storing one bit in one cell, one threshold distribution written in a cell needs to be narrowed. For this reason, the write speed becomes slow compared with a memory storing one bit.
Therefore, a high-level write is carried out as a whole, and thereby, it is possible to use a wide range of threshold voltages. This serves to perform high-speed write and to set many threshold levels. However, a high write voltage is required; for this reason, there is a need to provide a transistor that can endure a higher write voltage. In addition, the following problem arises; specifically, a peripheral circuit must be provided with a very large step-up circuit to generate the high voltage. Therefore, it is desired to provide a semiconductor memory device that can lower a write voltage and reduce a breakdown voltage of a transistor.